1. Technical Field
The present invention relates generally to computer memory design, and more specifically to reduction of coupling between bit lines.
2. Description of the Related Art
The central part of dynamic random access memory (DRAM) in a computer system is the memory cell array. Bits are stored in individually addressable unit memory cells, which are arranged together in an array of rows and columns. Memory cells are unambiguously determined by specifying the row and column number. The common unit memory cell is a 1-transistor-1-capacitor cell. This cell has a capacitor that holds data in the form of electric charges, and an access transistor that acts as a switch for selecting the capacitor. The gate of the transistor is connected to a word line. There are as many word lines as there are rows of memory cells. In addition to the word lines, the memory cell array also comprises bit line pairs, which are alternately connected to the sources of the access transistors. In single-port memory arrays, the number of bit line pairs is equal to the number of columns in the array. For dual-port memory arrays, there are two bit line pairs per column.
Coupling between the bit lines within a core cell, or with the bit line of an adjacent core cell, affects memory performance significantly, especially as the core cell dimensions get smaller the coupling effects increase. Coupling issues in dual-port memory cell arrays consist mainly of port-to-port coupling, cell-to-cell coupling, and coupling due to routing over memory. Thus far, a simple scheme has been used to address this issue in dual-port memories. This scheme involves twisting one of the bit line pairs. Such as solution addresses the port-to-port coupling within a cell but not necessarily all cell-to-cell coupling, or the coupling due to routing over memory.
Therefore, it would be desirable to have a method for reducing port-to-port, cell-to-cell, and over-route coupling in dual-port memory cell arrays.
The present invention provides a method for reducing electrical coupling within a computer multi-port memory cell array. The method comprises twisting complementary wires of a first, inner bit line pair in a first memory cell column, wherein the twisting reverses the complementary wires, and wherein the physical twisting occurs in odd numbered dummy rows, twice along a column. The complementary wires of a second, outer bit line pair in the same column, wherein the physical twisting occurs in even numbered dummy rows, once along the column. The complementary wires of a third, inner bit line pair in a second memory cell column are then twisted, wherein the physical twisting occurs in even numbered dummy rows, once along the column, and the complementary wires of a fourth, outer bit line pair in the second column are twisted in odd numbered dummy rows, twice along the column. In this manner the twisting of bit line pairs is alternated within each memory cell column, and the twisting pattern is alternated between columns, thus ensuring that the net distance between any given wire and each complementary wire of another bit pair is equal.